Jon, thanks for the description, but isn’t it sort of false advertising claiming the full well while binned on a CMOS sensor is the sum of the pixels since it’s digital? On a full frame CCD, it’s analog and actually summing charge of 4 pixels before being read out. But for a CMOS, even hardware binning is done digitally, so you aren’t adding charge. You are adding the pixel charge and readout noise after digitization. So, with such a low readout noise, I guess it’s basically the same. But the way they advertise it as a nearly 4x full well seems... weird. In a CCD, the effective pixel really is 4 pixels at an analog level, but not a CMOS. So, when they say full well they’re just saying equivalent charge from the 4 pixels summed assuming the electronics have a large enough bit depth? That’s what I was really trying to nail down, I guess a question of terminology.
It isn't really any different. Electrons, counts. Effectively the same thing. More signal. Summing electrons doesn't give you something that averaging pixels does not...except possibly less total read noise (depends on just how much you have with either camera). But when you start out with low read noise, you can still end up ahead even when you combine four units of read noise.
Lets just consider the simple summing in the driver type binning. You still take a 2x2 sample of images. Both CCD and CMOS here will add up to 50ke- per pixel, so both end up with 200ke- for saturated pixels. It is just that one actually works on electrons, the other works on ADU. With a 16-bit ADC then the 50ke- FWC would need a gain of ~0.77e-/ADU. So you end up with 262410 ADU total when you sum four pixels digitally. So you've got the same total signal now in your single output pixel... No loss here, just different representations.
When you sum four samples the noise grows in quadrature. Lets say the CCD has 9e-, the CMOS has 3e-. Well with four samples you have 6e- total read noise with the CMOS data, and 9e- total (maybe a bit more in the real world) with the CCD. From a dynamic range standpoint, you end up with 200,000/6 vs. 200,000/9, so the CMOS actually comes out slightly ahead here, 15.1 sops vs. 14.5 stops.
Now, if you average the digital data. You end up with a 50ke- FWC, but you also reduce the read noise...when you divide the signal, you are dividing both. So it is the same result in the end. You still have 15.1 stops of DR and a higher SNR, despite the fact that the actual number that represents your averaged signal is now back to 50ke-.
Yes, different approaches. But the end result is still the same. You are combining the individual signals of several pixels together to make a larger signal. Doesn't matter if you do that in charge space, voltage space, or digital space (the only real difference between the three is when read noise gets added and how...charge has the highest benefit from a read noise standpoint, voltage is in the middle, and digital gets all the read noise). Doesn't matter if you just sum, or average.
Edited by Jon Rista, 10 October 2019 - 02:15 AM.