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CMOS binning - IMX455

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#1 jfrech14

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Posted 10 October 2019 - 12:09 AM

I know there have been topics before, and I have always been under the impression that because of the on-pixel readout of CMOS sensors that binning doesn’t rest increase the full well. I was looking at the QHY600 specs and they claim nearly a 4x increase in full well when binned 2x2 which is something I would expect from a full frame sensor, but not a CMOS. Is this a specially designed sensor... or what is going on with these numbers? Are they just doing it as a dynamic range comparison and backtracking to a calculated equivalent full well or does the sensor have some new design where binning 2x2 is actually analog rather than digital? I can’t find a spec sheet for the sensor from Sony, only what I’ve seen around forums and on QHY’s website. 
 

Either way, looks like a pretty impressive camera and I’m glad Sony used 16-bit readout. The few specs available are impressive and I hope those getting the camera have patience because their computers are going to sweat when processing. 



#2 Jon Rista

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Posted 10 October 2019 - 12:30 AM

I know there have been topics before, and I have always been under the impression that because of the on-pixel readout of CMOS sensors that binning doesn’t rest increase the full well. I was looking at the QHY600 specs and they claim nearly a 4x increase in full well when binned 2x2 which is something I would expect from a full frame sensor, but not a CMOS. Is this a specially designed sensor... or what is going on with these numbers? Are they just doing it as a dynamic range comparison and backtracking to a calculated equivalent full well or does the sensor have some new design where binning 2x2 is actually analog rather than digital? I can’t find a spec sheet for the sensor from Sony, only what I’ve seen around forums and on QHY’s website. 
 

Either way, looks like a pretty impressive camera and I’m glad Sony used 16-bit readout. The few specs available are impressive and I hope those getting the camera have patience because their computers are going to sweat when processing. 

The maximum amount of charge involved in a "pixel" will always increase when binning. Even if it is just done in software, it will. Now, depending on the mechanism by which it is done, whether you can actually realize the full benefits of it will depend. But ignoring "downstream" limitations, consider what is going on.

 

You have say 50ke- maximum charge per pixel. So, on a per-pixel basis, binned or not, you can only hold 50ke-. If you sum the total charge in four of these pixels, what do you have? 50ke-? No, you have 200ke-! Each pixel can hold 50ke-, but four of them holds a total of 200ke-. 

 

So on to the downstream limitations. With hardware binning, you can have limitations that might affect whether you could actually store this much charge or not. Except for certain high end sensors, the wells that hold charge while it is being binned may not be able to handle 4x, 9x, etc. the maximum charge of a single pixel. Even if the wells can, the FD at the end of the pipeline and the rest of the circuitry after it may not be able to represent such a large amount of charge as a voltage. You might be able to handle 3x the amount of charge of a single pixel, rather than 4x, so you'l clip signals that end up larger than 3x the FWC of a single pixel.

 

When it comes to digitally summing or averaging the data. If you do not use a large enough register to hold the numbers while you sum pixels for digital binning or averaging, then again you will eventually clip. A driver that allows binning could be designed to use high bit depth counters, or floating point counters, to handle the binning process. So even though the hardware limitation of a single pixel may be 50ke-, if the driver uses variables of a high enough bit depth or precision, then it could be possible to sum 4, 9, or 16 pixels and not lose any of the information. 


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#3 jfrech14

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Posted 10 October 2019 - 12:42 AM

Jon, thanks for the description, but isn’t it sort of false advertising claiming the full well while binned on a CMOS sensor is the sum of the pixels since it’s digital? On a full frame CCD, it’s analog and actually summing charge of 4 pixels before being read out. But for a CMOS, even hardware binning is done digitally, so you aren’t adding charge. You are adding the pixel charge and readout noise after digitization. So, with such a low readout noise, I guess it’s basically the same. But the way they advertise it as a nearly 4x full well seems... weird. In a CCD, the effective pixel really is 4 pixels at an analog level, but not a CMOS. So, when they say full well they’re just saying equivalent charge from the 4 pixels summed assuming the electronics have a large enough bit depth? That’s what I was really trying to nail down, I guess a question of terminology.

#4 Jon Rista

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Posted 10 October 2019 - 02:11 AM

Jon, thanks for the description, but isn’t it sort of false advertising claiming the full well while binned on a CMOS sensor is the sum of the pixels since it’s digital? On a full frame CCD, it’s analog and actually summing charge of 4 pixels before being read out. But for a CMOS, even hardware binning is done digitally, so you aren’t adding charge. You are adding the pixel charge and readout noise after digitization. So, with such a low readout noise, I guess it’s basically the same. But the way they advertise it as a nearly 4x full well seems... weird. In a CCD, the effective pixel really is 4 pixels at an analog level, but not a CMOS. So, when they say full well they’re just saying equivalent charge from the 4 pixels summed assuming the electronics have a large enough bit depth? That’s what I was really trying to nail down, I guess a question of terminology.

It isn't really any different. Electrons, counts. Effectively the same thing. More signal. Summing electrons doesn't give you something that averaging pixels does not...except possibly less total read noise (depends on just how much you have with either camera). But when you start out with low read noise, you can still end up ahead even when you combine four units of read noise.

 

Lets just consider the simple summing in the driver type binning. You still take a 2x2 sample of images. Both CCD and CMOS here will add up to 50ke- per pixel, so both end up with 200ke- for saturated pixels. It is just that one actually works on electrons, the other works on ADU. With a 16-bit ADC then the 50ke- FWC would need a gain of ~0.77e-/ADU. So you end up with 262410 ADU total when you sum four pixels digitally. So you've got the same total signal now in your single output pixel... No loss here, just different representations. 

 

When you sum four samples the noise grows in quadrature. Lets say the CCD has 9e-, the CMOS has 3e-. Well with four samples you have 6e- total read noise with the CMOS data, and 9e- total (maybe a bit more in the real world) with the CCD. From a dynamic range standpoint, you end up with 200,000/6 vs. 200,000/9, so the CMOS actually comes out slightly ahead here, 15.1 sops vs. 14.5 stops. 

 

Now, if you average the digital data. You end up with a 50ke- FWC, but you also reduce the read noise...when you divide the signal, you are dividing both. So  it is the same result in the end. You still have 15.1 stops of DR and a higher SNR, despite the fact that the actual number that represents your averaged signal is now back to 50ke-. 

 

Yes, different approaches. But the end result is still the same. You are combining the individual signals of several pixels together to make a larger signal. Doesn't matter if you do that in charge space, voltage space, or digital space (the only real difference between the three is when read noise gets added and how...charge has the highest benefit from a read noise standpoint, voltage is in the middle, and digital gets all the read noise).  Doesn't matter if you just sum, or average. 


Edited by Jon Rista, 10 October 2019 - 02:15 AM.

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#5 deepanshu29

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Posted 10 October 2019 - 03:01 PM

Jon, 

Thanks for this explanation, I have been trying to understand binning for IMX455. So this is same as what we see on ASI1600/QHY163, except that we have a higher resolution ADC in IMX455.

 

If I understand correctly, for OSC IMX455, software will bin respective color pixels by adding nearest pixels of same color. I was thinking that for mono, the software will use the direct neighbors for monochrome, but from QHY explanation, it seems like it will use exact same map as color camera, that, to me, does not sound like right strategy for binning. 

If this is true, for monochrome it might be best to not to use binning while capturing but use resample to 50% size in post. 

 

From QHY600 FAQs - 

 

 

1. Does QHY600 support hardware binning?
The CMOS sensor itself has some binning function but it should not be the hardware binning (FD binning). And also the binning in the sensor is based on the location of the bayer color . it means it will binning with the same position of the same color.And for monochrom QHY600 sensor, it is still use such a position to do binning. So we think it is not a good solution for the monochrom binning.
And since the very low readout noise of the QHY600, so the digital binning may bring more advantage. First , it can increase the fullwell.  Binning at 2*2 will gives four times of the fullwell. Second, it will increase the AD sample depth. Binning at 2*2 will give 18bit data range.  For readout noise, the N*N digital binning will cause the readout noise become  SQR(N*N)= N times. For example, if the readout noise is 1.9e at 1*1 binning. The 2*2 digital binning readout noise will become  1.9*SQR(2*2)=3.8e.


#6 Jon Rista

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Posted 10 October 2019 - 04:31 PM

Jon, 

Thanks for this explanation, I have been trying to understand binning for IMX455. So this is same as what we see on ASI1600/QHY163, except that we have a higher resolution ADC in IMX455.

 

If I understand correctly, for OSC IMX455, software will bin respective color pixels by adding nearest pixels of same color. I was thinking that for mono, the software will use the direct neighbors for monochrome, but from QHY explanation, it seems like it will use exact same map as color camera, that, to me, does not sound like right strategy for binning. 

If this is true, for monochrome it might be best to not to use binning while capturing but use resample to 50% size in post. 

 

From QHY600 FAQs - 

I think they are just describing OSC binning. I would be blown away if a sensor like that, at that price point, did not do proper mono binning. I have little doubt that 2x2, 3x3 and 4x4 binning with mono will be neighboring pixels, and not a CFA-type sparse grid. 


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